Synopsys, Inc.
Rating
Accumulate
Adding on Dips — Active Accumulation
Combined average of Moat (AI Resilience), Growth, and Valuation scores.
Moat Score
Co-dominant EDA tools provider with deeply embedded software workflows used by every advanced chip designer; Ansys (now consolidated) extends the moat into multiphysics simulation. A July 2026 demo of an AI model taping out a toy 45nm design on open-source EDA sparked a moat-durability scare and a sharp selloff, but foundry-certified leading-edge flows (3nm/2nm, 3D-IC) remain non-substitutable.
Synopsys's moat is built on mission-critical software embedded in every advanced chip tape-out:
- Workflow Lock-In: Every modern chip from NVIDIA, Apple, AMD, and Qualcomm passes through Synopsys's design and verification flows. Switching tools mid-roadmap costs years and risks tape-out failure — making the leading-edge EDA toolchain effectively non-substitutable. Open-source EDA remains confined to legacy nodes (e.g. 45nm academic libraries); it has no foundry-certified path at 3nm/2nm.
- Ansys Multiphysics Stack: The ~$35B Ansys acquisition (closed mid-2025) bolts simulation (thermal, electromagnetic, structural) onto silicon design — enabling 'silicon-to-systems' workflows. Q2 FY2026 was the second full quarter of consolidation; joint products are shipping with monetization ramping in FY2027 and $400M revenue synergies targeted by year four. Antitrust-mandated divestitures are being worked through.
- AI Chip Design Tailwind: AI accelerator complexity (multi-die, 3D-IC, advanced packaging) drives EDA tool intensity. Synopsys's AI-powered DSO.ai and VSO.ai chip design copilots are gaining traction with 800+ commercial tape-outs, deepening usage per customer — the same AI wave that could eventually commoditise low-end design is, at the leading edge, increasing tool consumption.
Ten Moats Verdict
Synopsys remains broadly AI-resilient at the leading edge: rising chip complexity increases EDA tool intensity, and the Cadence duopoly is protected by tape-out risk aversion, foundry certification cycles, and decades of accumulated methodology IP (the strong transactionEmbedding, systemOfRecord, bundling and proprietaryData moats). The July 2026 Moonshot Kimi demo — an AI taping out a toy 45nm design on open-source EDA — is a genuine new signal that the businessLogic moat is exposed at the low end over a multi-year horizon, and is the moat's most-watched AI risk, but it does not touch foundry-certified 3nm/2nm flows today. Ansys extends the moat into multiphysics, subject to working through antitrust-mandated divestitures. Net: still an AI beneficiary at the advanced node, with a credible long-tail AI-disruption watch item at the commodity end.
Not applicable — Synopsys sells specialised engineering software to chip designers, not consumer-facing UI experiences.
EDA design rules, verification methodologies, and place-and-route algorithms encode decades of accumulated chip-design IP. A July 2026 AI demo (Moonshot Kimi) taped out a toy 45nm die on open-source tools, showing the low end is exposed over time — but foundry-certified leading-edge flows remain years beyond AI/open-source replication.
Not applicable — Synopsys does not derive moat from public data access.
EDA tool architects, verification methodology experts, and physical design engineers are extraordinarily scarce; Synopsys's R&D org embeds 30+ years of know-how unavailable elsewhere.
Full-flow bundle from RTL synthesis through physical design, verification, IP, and now Ansys multiphysics simulation creates an integrated stack competitors cannot easily unbundle.
Telemetry from 800+ commercial AI-driven tape-outs feeds DSO.ai and VSO.ai optimization models, generating compounding tool quality improvements unavailable to challengers.
EDA lacks an inherent certification moat; the swing factor is U.S.-China export policy. The May 2025 curbs on EDA sales to China were rescinded in July 2025, removing a ~10%-of-revenue headwind, but the geopolitical regime remains a two-sided risk rather than a durable lock-in.
Foundry partnerships (TSMC, Samsung, Intel) certify Synopsys reference flows for each new node, creating bilateral lock-in between fabs and design tools.
Every advanced chip tape-out runs Synopsys tools at multiple stages — switching mid-program risks tape-out delays worth tens of millions per slip.
Synopsys is the de facto system of record for chip design databases, verification environments, and IP libraries — the EDA toolchain IS the design history.
Combined average of Moat (AI Resilience), Growth, and Valuation scores.
Moat Score
Co-dominant EDA tools provider with deeply embedded software workflows used by every advanced chip designer; Ansys (now consolidated) extends the moat into multiphysics simulation. A July 2026 demo of an AI model taping out a toy 45nm design on open-source EDA sparked a moat-durability scare and a sharp selloff, but foundry-certified leading-edge flows (3nm/2nm, 3D-IC) remain non-substitutable.
Growth Score
Q2 FY2026 revenue of $2.276B (+42% YoY) reflected the second full quarter with Ansys consolidated. Core EDA grew ~8% organically on hardware-assisted verification and advanced-node demand, while Design IP ($454M, -6% YoY) confirmed its Q1 bottom and rose ~12% sequentially with sequential growth guided through the year. Management raised FY2026 guidance to $9.625–9.705B revenue and non-GAAP EPS of $14.72–14.80 (from $14.38–14.46), with ~$2B free cash flow and non-GAAP operating margin of ~39.5% (Design Automation segment margin 43.3%). Underlying organic growth runs ~8–12% with a ~20% non-GAAP EPS CAGR as Ansys synergies and AI-design product mix lift margins.
Valuation Score
At ~$384 (after a ~9.5% one-day drop on July 17 and ~23% off the May highs), SNPS trades at ~26× forward FY2026 non-GAAP EPS of ~$14.76 — below its ~30× five-year average — even as management *raised* both revenue and EPS guidance. The selloff was driven by an AI/open-source-EDA moat scare (Moonshot's Kimi 45nm demo), Ansys antitrust-divestiture concerns, and auto/industrial cyclical softness rather than by any deterioration in results. Base-case fair value of ~$470 implies ~22% upside; the de-rating has restored a margin of safety to a wide-moat compounder, tempered by the new AI-disruption tail risk. Sell-side consensus sits far higher (~$560 average, Buy).
The EDA Workflow Lock-In Moat
Synopsys's moat is built on mission-critical software embedded in every advanced chip tape-out:
- Workflow Lock-In: Every modern chip from NVIDIA, Apple, AMD, and Qualcomm passes through Synopsys's design and verification flows. Switching tools mid-roadmap costs years and risks tape-out failure — making the leading-edge EDA toolchain effectively non-substitutable. Open-source EDA remains confined to legacy nodes (e.g. 45nm academic libraries); it has no foundry-certified path at 3nm/2nm.
- Ansys Multiphysics Stack: The ~$35B Ansys acquisition (closed mid-2025) bolts simulation (thermal, electromagnetic, structural) onto silicon design — enabling 'silicon-to-systems' workflows. Q2 FY2026 was the second full quarter of consolidation; joint products are shipping with monetization ramping in FY2027 and $400M revenue synergies targeted by year four. Antitrust-mandated divestitures are being worked through.
- AI Chip Design Tailwind: AI accelerator complexity (multi-die, 3D-IC, advanced packaging) drives EDA tool intensity. Synopsys's AI-powered DSO.ai and VSO.ai chip design copilots are gaining traction with 800+ commercial tape-outs, deepening usage per customer — the same AI wave that could eventually commoditise low-end design is, at the leading edge, increasing tool consumption.
Ten Moats Verdict
Synopsys remains broadly AI-resilient at the leading edge: rising chip complexity increases EDA tool intensity, and the Cadence duopoly is protected by tape-out risk aversion, foundry certification cycles, and decades of accumulated methodology IP (the strong transactionEmbedding, systemOfRecord, bundling and proprietaryData moats). The July 2026 Moonshot Kimi demo — an AI taping out a toy 45nm design on open-source EDA — is a genuine new signal that the businessLogic moat is exposed at the low end over a multi-year horizon, and is the moat's most-watched AI risk, but it does not touch foundry-certified 3nm/2nm flows today. Ansys extends the moat into multiphysics, subject to working through antitrust-mandated divestitures. Net: still an AI beneficiary at the advanced node, with a credible long-tail AI-disruption watch item at the commodity end.
Not applicable — Synopsys sells specialised engineering software to chip designers, not consumer-facing UI experiences.
EDA design rules, verification methodologies, and place-and-route algorithms encode decades of accumulated chip-design IP. A July 2026 AI demo (Moonshot Kimi) taped out a toy 45nm die on open-source tools, showing the low end is exposed over time — but foundry-certified leading-edge flows remain years beyond AI/open-source replication.
Not applicable — Synopsys does not derive moat from public data access.
EDA tool architects, verification methodology experts, and physical design engineers are extraordinarily scarce; Synopsys's R&D org embeds 30+ years of know-how unavailable elsewhere.
Full-flow bundle from RTL synthesis through physical design, verification, IP, and now Ansys multiphysics simulation creates an integrated stack competitors cannot easily unbundle.
Telemetry from 800+ commercial AI-driven tape-outs feeds DSO.ai and VSO.ai optimization models, generating compounding tool quality improvements unavailable to challengers.
EDA lacks an inherent certification moat; the swing factor is U.S.-China export policy. The May 2025 curbs on EDA sales to China were rescinded in July 2025, removing a ~10%-of-revenue headwind, but the geopolitical regime remains a two-sided risk rather than a durable lock-in.
Foundry partnerships (TSMC, Samsung, Intel) certify Synopsys reference flows for each new node, creating bilateral lock-in between fabs and design tools.
Every advanced chip tape-out runs Synopsys tools at multiple stages — switching mid-program risks tape-out delays worth tens of millions per slip.
Synopsys is the de facto system of record for chip design databases, verification environments, and IP libraries — the EDA toolchain IS the design history.
Growth Analysis
Growth Drivers
Key Risk
If open-source and AI-generated EDA flows (e.g. Moonshot's Kimi chip-design demo) move up from academic 45nm nodes toward commercial advanced nodes within 2–3 years, the switching-cost moat and per-design tool intensity erode; nearer term, Ansys antitrust divestitures or an auto/industrial capex slowdown could pressure the synergy narrative and compress the multiple
Score Derivation
76.4 base + 1.3 trajectory + 4 margin − 5 risk = 77
Base 76 (organic EDA ~8% and blended sustainable ~10–13% with ~20% EPS CAGR — mid 8–15% bracket, softer than prior 10–12% read) + 1 driver mix (DA accelerating vs IP recovering) + 4 margin expanding + 3 TAM expansion (multiphysics) − 5 moderate key risk (AI/open-source EDA overhang + Ansys divestitures) = 79
Price Scenarios (12–24 Months)
Valuation Multiples
| Trailing P/E (GAAP) | ~100×+ |
| Forward P/E (NTM) | ~26× |
| PEG Ratio | ~1.3× |
| Price / Sales (NTM) | ~7.5× |
| Price / FCF | ~37× |
After the July selloff SNPS trades at ~26× forward P/E, a de-rate below its ~30× five-year average and its cheapest in years despite raised guidance. PEG of ~1.3× is reasonable for a recurring-license EDA franchise with ~95% renewal rates and structural AI-design tailwinds. The wide gap between distorted trailing GAAP (~100×+) and forward non-GAAP (~26×) is an Ansys-amortization artefact, not deteriorating economics — the valuation score reflects a genuinely more attractive entry, discounted for the AI-disruption and divestiture overhangs.
Approximate figures as of July 2026.
Where We Are vs Targets
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The AI/open-source-EDA disruption narrative gains credibility, Ansys divestitures dilute deal value, and an auto/industrial slowdown pressures software licensing — compressing the multiple to a trough ~22× on FY2026 EPS.
- Open-source and AI-generated EDA flows demonstrate a credible path toward commercial nodes, prompting the market to permanently haircut long-run per-design tool intensity
- Antitrust-mandated Ansys divestitures prove larger than expected, deferring the $400M synergy target and forcing a re-rating toward 20–22× forward
- Cadence captures incremental share at 3nm/2nm verification while a cyclical downturn in auto/industrial multiphysics demand slows Ansys growth to low single digits
The AI-disruption fear proves overblown at leading-edge nodes, guidance holds and rises, Design IP recovers through H2, and Ansys synergies begin monetizing in FY2027 — supporting ~27× FY2027 non-GAAP EPS.
- FY2026 non-GAAP EPS lands in the raised $14.72–14.80 range with non-GAAP operating margin ~40%, validating cost-synergy execution
- Design IP delivers the guided sequential recovery off its Q1 bottom, and joint Synopsys-Ansys products book initial monetization in FY2027 toward $400M revenue synergies by year four
- AI-driven DSO.ai and VSO.ai adoption expands EDA wallet share per customer, lifting organic Design Automation growth toward low-double-digits and the multiple back toward its ~30× historical average
AI chip-design intensity re-accelerates organic EDA toward 12–15%, Ansys synergies ramp ahead of plan, and the multiphysics-plus-silicon bundle commands premium pricing — re-rating the multiple back toward 34× forward, roughly sell-side consensus.
- Joint Synopsys-Ansys workflows are adopted by hyperscaler in-house silicon teams (Google TPU, Amazon Trainium, Meta MTIA) at premium ASPs, accelerating revenue synergies above $500M by FY2028
- Organic EDA growth inflects toward 15% as 3D-IC and chiplet packaging drive ~2× tool intensity per design, expanding TAM beyond the historic ~10% trajectory and de-risking the AI-disruption thesis
- Operating margin reaches 43%+ by FY2027 as integration costs roll off and AI productivity tools lift R&D efficiency, pushing non-GAAP EPS toward $18 and re-rating the stock toward analyst targets